This invention relates to semiconductor devices, and more particularly, to semiconductor transistors including an LDMOS (lateral double-diffused metal oxide semiconductor) device.
Battery-operated electronic systems such as notebook personal computers, personal digital assistants, and wireless communication devices often use power MOS (metal oxide semiconductor) devices as low on-resistance electronic switches for distributing battery power. For battery-operated application, low on-resistance can be particularly important to ensure as little power consumption to the battery as possible. This ensures long battery life.
DMOS devices are xe2x80x9cdouble diffusedxe2x80x9d MOS devices. A DMOS device is characterized by a source region and a back gate region, which are diffused at the same time. The back gate region is sometimes referred to as a Dwell (double diffused well) region. The channel is formed by the difference in the two diffusions, rather than by separate implantation. DMOS devices have the advantage of decreasing the length of the channels, thus providing low-power dissipation and high-speed capability.
DMOS devices may have either lateral or vertical configurations. A DMOS device having a lateral configuration (referred to herein as an LDMOS), has its source and drain at the surface of the semiconductor wafer. Thus, the current is lateral. Desired characteristics of an LDMOS are a high breakdown voltage, BV, and a low specific on-resistance.
A conventional LDMOS configuration is shown at 10 in FIG. 1, with a source region shown at 11, a drain region at 12, a gate region at 13, and a backgate region at 15. Since the drain region 12 is integral to the NBL 14, then it cannot be isolated in its own tank from the parasitic collection guardring consisting of n-type buried layer (NBL) 14 and DEEP N+ well 16. Therefore, when in use as a low side device driving an inductive load, as shown schematically in FIG. 2, then when device 10 is switched off or to a condition when the drain 12 of the device 10 consequently becomes negative, the integral parasitic diode D2 from P-epi 18/substrate 20 to Deep N+ 16, and the parasitic diode D1 from the p-type backgate 24 to N-region 22 both conduct. As a consequence of this conduction, the P backgate 24, P-epi 18 and substrate 20 build up a large amount of minority charge, in this case, electrons. When switched back on, or changed to a blocking state, the electrons either have to be recombined or collected by the drift field set up with an N type region that is positively biased. In the case of FIG. 1, the electrons in the P region 24 will have to recombine and will thus create a long recovery time. In the regions 18 and 20 the electrons will get collected by some other N region.
This method of collection can create a very large problem of classical latch-up if collection efficiency is low. Additionally, the extra collection guardring 14 and 16 uses a lot of silicon area and it is desired to eliminate this area usage.
An optimized tankxe2x80x94isolated drain device that overcomes these problems is needed in an advanced CMOS process capable of very high current operating conditions and switching through required breakdown. The improved device should reduce the minority carrier lifetime to improve switching speed. The on resistance performance of this device needs to be extremely competitive to enable the highest current possible at very low drive voltage in the smallest form factor package.
The present invention achieves technical advantages as a distributed power device including a plurality of tank regions separated from one another by a deep n-type region, and having formed in each tank region a plurality of transistors. The plurality of transistors in each tank region are interconnected to transistors in other tank regions to form a large power FET, whereby the deep n-type regions isolate the tank regions from one another. A first parasitic diode is defined from each tank region to a buried layer, and a second parasitic diode is defined between the buried layer and a substrate. Advantageously, the deep n-type regions distribute the first and second parasitic diodes with respect to the plurality of tank regions, preferably comprised of a P-epi tank. The deep n-type regions also distribute the resistance of an NBL layer formed under the tank regions. The distributed parasitic diodes and resistance of the NBL layer advantageously provides that the parasitic diode between the NBL layer and the substrate will never be forward biased. In addition, each of the tank regions reduces the minority carrier lifetime of the transistors to provide increased switching speed of the large power FET. The reduced minority carrier lifetime is achieved through the use of an additional heavily doped p-type region disposed proximate the drains of the transistors and extending proximate the drains of each of the transistors within the particular tank region.
Preferably, the n-type regions are tied to ground to collect the minority carriers when utilized as a low side power FET, and are preferably tied to a positive potential when utilized as a high side power FET.
The second p-type region preferably has a higher dopant concentration than the P-epi tank, yet has a lower concentration than a first p-type region defined proximate the source of each of the transistors.